Synthesis of 2-level combinatorial circuits with PKmin

Zbigniew Kokosiński,

Tomasz Michalski


In this paper a new design tool is presented that is useful in automated synthesis of combinatorial logic. PKmin program is devoted for synthesis of 2-level circuits composed of gates and PLAs, multi-level circuits and a functional decomposition of logical functions for LUT-based logic implementations in FPGA. It has been built on the basis of the research conducted at Cracow University of Technology. In the paper design algorithms implemented in PKmin are mutually compared. Then, an experimental efficiency comparison of gate and PLA-based 2-level synthesis with PKmin and Espresso design tools is reported.

Słowa kluczowe: combinatorial logic, PLD, logical function minimization, Kapralski algorithm, Kazakov algorithm, PKmin, Espresso